| 现代电子系统规划中，经常将DDR内存接口分成内存控制逻辑（MC，Memory Controller）和物理层接口（PHY，Physical Interface）两个部分。这两个部分侧重点不一样，往往需要不一样的规划技巧和规划经验。随着IP（intellectual property）厂商的发展，越来越多的工程师选择在规划中采用第三方的IP核，来加速项目进度。这就带了问题，由于MC和PHY两部分的规划者往往并不相同，为了能够实现两者之间的标准互联，需要一种MC与PHY之间的标准通信接口。而DFI就是这样的一种规范。DFI标准的提出旨在定义一个MC与PHY之间的通用接口，以提升独立模块（IP核等）的复用率，进而降低成本，缩减项目周期。 DFI标准已经被越来越多的半导体厂商、IP核开发商、EDA厂商所接受并认可。现在来说，其会员主要有：ARM, Avago, Cadence, Intel, Samsung, ST Microelectronics, Synopsys and Uniquify。FPGA厂商Lattice在提提供的Demo（参考规划）和IP中，也采用了DFI和MC&PHY的规划模式。 英语不错的童鞋，可以看原文： About DFI Introduction The memory controller logic and PHY interface represent the two primary design elements in DDR memory systems, which are used in virtually all electronic system designs, from cellphones and set-top boxes, to computers and network routers. These two components of the memory system require a uniquely different set of engineering skills, tools and methodologies, and thus, are often developed by separate engineering teams, or are acquired from different third-party design intellectual property (IP) vendors. Consequently, the lack of a standard interface between the two design elements has become the source of significant integration and verification costs by systems developers, memory controller vendors, and PHY providers. The goal of the DFI specification is to define a common interface between the memory controller logic and the PHY interface in order to reduce cost, time-to-market, and increase the potential for reuse of the individual components that make up the memory system. The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including: ARM, Avago, Cadence, Intel, Samsung, ST Microelectronics, Synopsys and Uniquify. The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices. DFI主要提供的接口如下图：  |
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